Scan based techniques offer an efficient alternative to achieve high fault coverage compared to the functional pattern based testing. As the design size increases and multi-core SoCs (system-on-chip) becomes essential to drive high speed applications, test data volume and test application time grow unwieldy even in the highly efficient and balanced scan based designs. Scan compression technique is so far, the best technique for test data volume as well as test time reduction during pattern execution of scan inserted designs. Few compression techniques that are implemented in SoCs include broadcast or Illinois architecture, muxed and XOR architecture or MISR (multiple input shift register) based compression architecture. The problem in today's power consuming devices is to handle the leakage power. Efforts are made to use ultra-low leakage library (ULL) cells. A ULL cell library based IO (input/output) receives a scan input on an input terminal and generates a scan output on an output terminal. The ULL cell library based IOs have very high inertial delay on clock and data path at the output terminal that can go as high as the order of 30 ns. The input terminal of these IOs is not affected by this timing issue as the inertial delay between clock and data path is very low. Under such conditions, it is not possible to drive scan operation at higher frequency like 30 MHz or higher. Even though VLCT (very low cost tester) can support data to be driven at higher clock frequency but slower scan output is the bottle neck to the operation. As a result scan operation is not executed at optimal frequency resulting in higher test time.